* lcd.asm
* RT Praktikum FH-Augsburg (Bayer, Hoegl)
* Steve Moser, Marcus Stegner
* Write text to 16x2 LCD display.


* Addressmap
RAM	EQU	$0		;RAM section
STACK	EQU	RAM+$800	;Stack section
PGM	EQU	RAM+$C00	;Program start
ROM	EQU	$800000		;ROM section
STACKSZ EQU	1024		;Max stack size

* Definitions
*
* 68332 global register definitions
*
* SIM
SIMCR   EQU     $FFFA00         ;SIM Configuration Register
SYPCR   EQU     $FFFA20         ;System Protection Register
CSBARBT EQU     $FFFA48         ;Chip Select Base Address Boot Register
CSBAR0  EQU     $FFFA4C         ;Chip Select Base Address Register 0

CSBAR5	EQU	$FFFA60		;LCD connected to CS5
CSOR5	EQU	$FFFA62

CSPAR0	EQU	$FFFA44		;Chip Select Pin Assignment

*PORT E
PEPAR	EQU     $FFFA16        	;Pin Assignment Register
DDRE	EQU     $FFFA14        	;Data Direction Register
PORTE	EQU     $FFFA12        	;Port E is decoded on 2

*PORT F
PFPAR	EQU     $FFFA1E        	;Pin Assignment Register
DDRF	EQU     $FFFA1C        	;Data Direction Register
PORTF	EQU     $FFFA1A        	;Port F is decoded on 2  

*LCD
LCD_IR	EQU	$200000		;LCD Instruction Register
LCD_DR	EQU	$200001		;LCD Data Register

* Place FEPROM at $800000, because unused
	org 	CSBARBT		;set on CSBARBT
	dc.w	$8003		;at 8M, size 64KB

* Place ext. RAM at $0, 256KB, 0WS
	org     CSBAR0		;Set on SIM CSs
	dc.w	$0005		;CSBAR0, ext. RAM_RD
	dc.w	$6830		;CSOR0	
	dc.w	$0005		;CSBAR1, ext. RAM_WR_LO
	dc.w	$3030		;CSOR1		
	dc.w	$0005		;CSBAR2, ext. RAM_WR_HI
	dc.w	$5030		;CSOR2

* Initialize SIM and system protection

* Switch off watchdogs, also while FREEZE is active
	org	SIMCR
	dc.w	$60CF		;FREEZE settings

	org	SYPCR
	dc.w	$0000		;no system protection

* Define Stack 
	org     STACK		;Stack from STACK to STACK + STACKSZ
sseg	ds.b    STACKSZ		

cseg	org     PGM         	;Programcode at $C00

* Initialize stack pointer
	move.l	#sseg+STACKSZ,a7 ;load stack pointer

* Initial Program Counter is initialized by the corresponding 
* DO-File

* Initialize Port E
	move.w	#$0000,PEPAR	;I/O instead of systembus
	move.w 	#$000F,DDRE	;4 bit as output

* Initialize Port F
	move.w	#$0000,PFPAR	;I/O instead of systembus
	move.w 	#$0000,DDRF	;all 8 bit as input

* Init LCD Chipselect
	or.w	#$2000,CSPAR0	;CS5 Enable
	move.w	#$2000,CSBAR5	;Basisadresse LCD, 2K Block
	move.w	#$7D30,CSOR5	;CS Options
	
main
        bsr     main_own
forever bra     forever


* Initialize the LCD display
lcd_init
	move.b	#$38,LCD_IR     ; DL=1 (8-Bit), N=1, F=0
	bsr	lcd_busy
	move.b	#$0f,LCD_IR	; 1 D C B (Display, Cursor, Blink)
	bsr	lcd_busy
	move.b	#$01,LCD_IR	; Clear Display, Cursor Home
	bsr	lcd_busy
	move.b	#$06,LCD_IR	; 1 I/D S 
	bsr	lcd_busy     
	rts

* Write a data character to the LCD display
lcd_char	
        move.b	d0,LCD_DR
	bsr	lcd_busy
	rts

* Wait until LCD display is ready for another read/write cycle
lcd_busy	
        btst	#7,LCD_IR       ; Bit 7 ist 1 falls LCD Busy
	bne.b	lcd_busy	; Z-Bit ist invertiertes Bit-7
	rts

* Move cursor one position to the right
cu_right  
        move.b  #$14,LCD_IR
        bsr     lcd_busy
        rts



*----------------------------------------------------------------
*CLRDSP
*	move.b	#$01,LCD_IR	; Clear Display, Cursor Home
*	bsr	lcd_busy
*	rts
*________________________________________________________________
*----------------------------------------------------------------
*SHUTDSP
*	
*	move.b	#$08,LCD_IR
*	bsr	lcd_busy
*	rts
*________________________________________________________________
*----------------------------------------------------------------
*SHOWDSP
*	move.b	#$0C,LCD_IR
*	bsr	lcd_busy
*	rts
*________________________________________________________________

*Own main
main_own

QSMCR   equ     $FFFC00         ;QSM configuration register (um in den supv zu switchen)
SCSR    equ     $FFFC0C         ;sci-bus status register (data there ?)
SCDR    equ     $FFFC0E         ;sci-bus data register (write and catch data)
SCCR0   equ     $FFFC08         ;baud-rate sci-control-register 0
SCCR1   equ     $FFFC0A         ;sci-control-register 1 for configuring parity/stop/loop/wake a.s.o.
	
	move.w	#0,d0
        bsr     lcd_init

        move.w  #$37,SCCR0      ;baudrate in sccr0 einstellen
        move.w  #12,SCCR1	;no parity, 8 bit im sccr1
        move.w  #$0000,QSMCR    ;busoperation ( supervisor-mode),eigentlich bit 0 niederes byte supv


loop    btst.b  #6,SCSR+1       ;prüfe auf 0 ab, wenn ja (keine neuen daten),wiederhole 
				;TDRE transmission data received empty bit
        beq     loop		;wenn ja (neue daten vorhanden),gehe weiter (bit == 1)
        move.b  SCDR+1,d0       ;schreibe in register das erhaltene zeichen
        
        bsr     lcd_char        ;gib das zeichen am lcd aus 


test    btst.b  #0,SCSR         ;transmission data register flag 0==daten werden noch gesendet
        beq     test            ;warte
        move.b  d0,SCDR+1       ;switch auf senden damit echo auf hyperterminal
        bra     loop            ;zurück und auf neue daten warten



* Wait loop
                  
*wait
*	move.W	#$9000,D3	;Zaehler aussen -->Testpunkt (SP,PC, D3) 
*	move.W	#$FFFF,D2	;Zaehler innen
*LOOP1	dbra	D2,LOOP1	
*LOOP2	dbra	D3,LOOP2	
*	rts                     ;return  	-->Testpunkt (D2,D3)

end